This invention relates in general to devices which are capable of synthesizing a plurality of frequencies from a single stable source frequency, and more particularly to such devices which generate sinusoidal signals from stored digital samples.
Digital frequency synthesizers of various forms and designs are known in the art, and excellent treatises on the subject have been published. One such treatise is an article entitled "A Digital Frequency Synthesizer" published in IEEE Transactions On Audio and Electroacoustics, Volume AU-19, No. 1, March 1971, pages 48-56, and authored by Tierney, et al. The treatise shows an input control word, representing the desired frequency, being stored in a register and used to update an accumulator each period of a stable source frequency. The accumulator addresses a read-only memory (ROM) containing samples of sinusoidal functions. Digital data from the ROM is converted to an analog signal which is then low-pass filtered. U.S. Pat. No. 3,735,269 by Jackson also mentions the Tierney, et al., treatise in its presentation of a digital frequency synthesizer. The Jackson synthesizer discloses the same basic elements as the treatise. Other common elements are some form of a complementor between the accumulator and the ROM to enable the devices to take advantage of the symmetries in sinusoidal functions, and thereby reducing the amount of memory required to store the samples.
Both the Jackson and the Tierney, et al., devices were designed at a time when the only available semiconductor ROM's were relatively expensive and small in capacity, and high-speed ROM's were even more so. At that time it was highly desirable to create designs which minimized ROM requirements, and the Jackson and Tierney, et al., devices reflect that minimization.
This invention takes unique advantage of the current availability of relatively inexpensive and large capacity ROM's. By using such a ROM, the complexity of the circuit and the number of components used to perform the same or similar functions are greatly reduced. This is so because samples covering an entire period of a sinusoidal function are stored in the ROM rather than one-half or one-quarter of a period as in the prior art. This enables new architecture that substantially reduces circuit complexity and costs.
In addition, this invention utilizes an entirely binary-coded decimal (BCD) system to address the read-only memory which essentially functions as a BCD to sinusoidal function conversion table. The use of an entirely BCD front-end serves to reduce the complexity of the circuit over the circuits presented by Jackson and Tierney, et al. The BCD front-end and the storage of an entire period also enables the use of an industry standard frequency reference, such as 10 Mhz, rather than the 8 Mhz frequency reference used by Jackson, which is non-standard in the instrumentation industry.
The instrumentation industry is pertinent to this invention because frequency synthesizers of the type disclosed herein are most frequently used in or with instrumentation, the vast majority of which have a 10 Mhz internal clock or provide 10 Mhz as an excitation frequency. 10 Mhz is the industry standard for electronic instrumentation requiring accurate frequency synthesis, such as, frequency synthesizers, counters, spectrum analyzers and network analyzers.
The Jackson and the Tierney, et al., devices are inherently limited to source frequencies evenly divisible by 4, such as the 8 Mhz preferred by Jackson, because their front-ends are not entirely BCD and because they store only a symmetrical portion of a sinusoidal function, not the entire function. With a reference frequency of 10 Mhz, their resolution would be an odd number adding distortion.
A further advantage of this invention is that an entire sinusoidal function is stored in the ROM and used during the synthesis. This has the effect of a substantial reduction in circuit complexity.
Other advantages and attributes of this invention will be readily discernible upon a reading of the text hereinafter.